This invention generally relates to high-bit density dynamic random access memory devices (DRAMs) of the type which use word lines shunted by metal-wiring, and more specifically, to such DRAM devices which compensate for any imbalance of capacitance developed between the bit lines adjacent to the metal-wire shunting.
In the past years, the development of the DRAM device has steadily increased resulting in a similar increase in its bit density. Following current trends, the bit-density magnitude of the DRAM device increases by a factor of four every two to three years of development.
Such an increase in bit density has led to an increase in product applications for the DRAM, especially since the introduction of the 1 Megabyte DRAM chip.
The use of metal-wire shunting in DRAMs is known. DRAMs having word-lines shunted by metal wiring have proven to be effective in reducing the propagation delay time of a signal moving along the length of a word line. It is important to compensate for the increasing propagation delay time due to increasing bit density.
FIGS. 1 and 2 are conceptual schematics of a portion of the architecture PRIOR ART DRAM devices showing the intersection of polysilicon word-lines, bit-lines and a metal word-line shunt. The metal word lines are arranged in parallel over the polysilicon word lines. At predetermined intervals between bit-line columns, the metal word lines make contact with the polysilicon word lines, at metal shunting zones 11. Intersecting both metal and polysilicon word-lines are the bit lines which are paired off to define the bit-line columns. Located at one end of each bit-line pair is connected a bit-line sense amplifier 12.
A DRAM device may include a metal shunting zone 11 every 64 columns (bit-line pairs). The propagation delay time of the metal wire word lines can be ignored, in this case, because the resistance of the metal is about 0.001 the resistance of the polysilicon word lines. Therefore, the propagation delay time of the word lines of this DRAM depend on the resistance of the word-line driver and the propagation delay time of the polysilicon word lines between the metal shunt zones.
A characteristic delay time (TD) is expressed as the following formula: EQU TD=1.02.times.Rwl.times.Cwl+2.21.times.Rd.times.Cw
where,
Rwl=the resistance of entire word-lines; PA0 Cwl=the capacitance of entire word-lines; and PA0 Rd=the resistance of the word-line driver.
As previously discussed, metal-wire shunting of the word-lines in a DRAM device beneficially reduces the propagation delay time of the word-lines, but the use of metal-wire shunting also includes certain disadvantages. One such disadvantage is that the area of the DRAM chip is forced to increase due to the additional area needed to accommodate the contact points between the polysilicon and metal word-lines. Another disadvantage to the use of metal-wire shunting is that each metal shunting zone 11 adversely effects the operation of any adjacent bit-line sense amplifiers. Referring to PRIOR ART FIGS. 1 and 2, the bit-lines 1 and 2, which are adjacent to the metal shunting zone 11, will have a resulting capacitance different to the capacitance of the more remote bit-lines on the DRAM device. This difference in capacitance between the bit-lines resides in a coupling capacitance. Bit-lines positioned remote of the metal shunting zone 11 will include a coupling capacitance value of 2 Cc resulting from a coupling influence of left and right neighboring bit-lines. Whereas the bit-lines 1 and 2 which lie adjacent the metal shunting zone 11 have a coupling capacitance value of 1 Cc due to their single respective neighbor (i.e., bit-line has only a left neighbor and bit-line 2 has only a right one).
This imbalance of capacitance of bit-lines 1 and 2 prevents their connected sense amplifiers from operating as well as the other, more remote sensing amplifiers. Referring to PRIOR ART FIG. 3, the sensing amplifier 12 connected to bit-lines located adjacent to the metal shunting zone 11 experiences a capacitance imbalance as much as 1 Cc. Each pair of sensing amplifiers 12 adjacent each metal shunting zone 11 of the DRAM device will be effected and will not operate properly. The accumulated result will lower the operational characteristics of the entire DRAM itself.
This capacitance imbalance problem has been recognized by the prior art and one resulting solution is illustrated in PRIOR ART FIG. 4. Here, two dummy bit-lines 91 and 92 are supplied on either side of the metal shunting zone 11 and connected to a common ground. Each dummy bit-line 91, 92 did allow the nearest functional bit-line pair and the corresponding sense amplifier 12 to operate with a balanced coupling capacitance, however such dummy bit-lines required additional space which was not readily available on the DRAM chip. For example, if a pitch of a bit-line is represented by "Lb", then in order to accommodate the dummy bit-lines the chip area would have to increase as much as 2 Lb for every metal shunt zone used.
It is an object of the present invention to provide a high bit density DRAM device of the type including metal-wire shunting wherein bit-line pairs both remote from and adjacent to the metal shunt zones include balanced capacitive coupling without jeopardizing the overall bit density of the DRAM device.